The present disclosure relates to a flash memory device and a method of manufacturing the flash memory device.
A flash memory device is a non-volatile storage medium and thus no power is needed to maintain data stored therein. In addition, the flash memory device has an advantage of offering relatively fast process speeds such as fast programming speed, fast read access speed, and fast erasing speed.
For the flash memory device, a semiconductor device using a silicon-oxide-nitride-oxide-silicon (SONOS) structure is often used. Many masks for forming patterns are used to manufacture the SONOS memory device.
Charges injected into a dielectric (e.g., a nitride layer) of the SONOS memory device are trapped by being dangling-bonded on the silicon substrate. Electrons are injected during a programming process and holes are injected during an erasing process. When the electrons and holes are injected into the dielectric, an energy barrier of the holes is higher than that of the electrons. Accordingly, the SONOS memory device has lower erasing process efficiency. This is one important characteristic of memory cells.
The erasing process method is roughly categorized into a Fowler-Nordeim (FN) tunneling method and a band-to-band-tunneling (BTBT) hot hole injection method. The method of the erasing process is determined depending on a method of a programming process.
For the programming process using the FN tunneling method, since the electrons are distributed throughout a channel, the erasing process must be also performed by the FN tunneling method to erase the electrons. In this case, in order to effectively erase a cell, a tunnel oxide of the structure must be thinly formed, such as having a thickness of about 20˜30 Å. This deteriorates a retention property of the electrons. However, when a thickness of the tunnel oxide increases, an erasing time increases or a voltage necessary to perform the erasing process increases, and a back-tunneling phenomenon where the electrons are introduced from a gate to the insulation layer (tunnel oxide) occurs.
For the programming process using a channel hot electron (CHE) method, since the electrons are distributed in the gate and an ion implantation area of a side surface of the gate, the erasing process is performed by the BTBT hot hole injection method. In this case, since the distribution of the electrons and charges in the ion injection area becomes an important factor determining a cell characteristic, a junction structure of the ion injection area and operating voltage application condition could be important.
Meanwhile, since the charges are distributed within 100 nm of the ion injection area, the insulation area outside of the charge distribution area is unnecessary. That is, the insulation area outside of the charge distribution area causes the increase of erasing voltage and the decrease of cell current. Therefore, a technique for reducing a length of the dielectric by removing an unnecessary side end of the insulation area and a technique for self-aligning a middle portion of the dielectric by dividing a select/memory gate into two sections have been proposed.
However, the former case has a limitation in that, since it is difficult to define a critical dimension and removal area in a photolithography process, chips have different properties. The latter case has a limitation in that the process is complicated and the cell property may be deteriorated.
Further, when the memory gate is formed after the select gate, an L-shaped dielectric is formed near the select gate, and the electrons are injected through a source side injection (SSI) process, the electrons trapped at a corner portion of the dielectric are not erased. Thus, an endurance property is deteriorated.